000077996 001__ 77996 000077996 005__ 20190226114815.0 000077996 037__ $$aTAZ-TFG-2018-1429 000077996 041__ $$aeng 000077996 1001_ $$aEdo Vivancos, Isak 000077996 24200 $$aFPGA-based Accelerators for cryptography 000077996 24500 $$aFPGA-based Accelerators for cryptography 000077996 260__ $$aZaragoza$$bUniversidad de Zaragoza$$c2018 000077996 506__ $$aby-nc-sa$$bCreative Commons$$c3.0$$uhttp://creativecommons.org/licenses/by-nc-sa/3.0/ 000077996 520__ $$aCryptography involves mathematical theory and encryption meth- ods. Cryptography algorithms are designed around computational hardness assumptions. This leads to heavy computational intensive algorithms. Sometimes a software approach could not be enough, but a hardware approach could be very complex. In this project, we present a halfway between software and hardware approach using an FPGA. The intended outcome of the project is the design and development of two hardware-based accelerators for cryptography that can be dynamically loaded into the FPGA. Mul- tiple approaches are presented during the project in order to design and test the accelerators. 000077996 521__ $$aGraduado en Ingeniería Informática 000077996 540__ $$aDerechos regulados por licencia Creative Commons 000077996 700__ $$aNannarelli, Alberto$$edir. 000077996 7102_ $$aUniversidad de Zaragoza$$bInformática e Ingeniería de Sistemas$$cArquitectura y Tecnología de Computadores 000077996 7202_ $$aSuárez Gracia, Darío$$eponente 000077996 8560_ $$f682405@celes.unizar.es 000077996 8564_ $$s2222625$$uhttps://zaguan.unizar.es/record/77996/files/TAZ-TFG-2018-1429.pdf$$yMemoria (eng) 000077996 909CO $$ooai:zaguan.unizar.es:77996$$pdriver$$ptrabajos-fin-grado 000077996 950__ $$a 000077996 951__ $$adeposita:2019-02-26 000077996 980__ $$aTAZ$$bTFG$$cEINA 000077996 999__ $$a20180615132629.CREATION_DATE